With the development of science and technology, flat panel display devices e.g., liquid crystal display devices have many advantages of high display quality, small volume, light weight and wide application range and thus are widely used in consumer electronics products such as mobile phones, laptop computers, desktop computers and televisions, etc. Moreover, the flat panel display devices have evolved into a mainstream display devices in place of cathode ray tube (CRT) display devices.
In order to reduce the cost of flat panel display device, gate-on array (abbreviated as GOA) driving and half-source driving (abbreviated as HSD) technologies have been proposed. It is well-known that, the GOA driving circuit is directly manufactured on a display panel like the manufacture of pixels; and in a display panel with HSD structure, pixels electrically coupled to a same data line would be arranged two sides of the data line e.g., in zigzag manner. Generally, the conventional GOA driving circuit includes multiple shift registers connected in cascade for sequentially outputting multiple gate driving pulses, and FIG. 1 illustrates a single stage shift register SR(n) in the cascade-connected shift registers. In particular, the shift register SR(n) includes transistors T11, T12, T21 and a pull-down circuit 100. The drain/source of the transistor T12 receives a clock signal CK(n−1), and the gate of the transistor T12 receives a control signal Q(n−1) to determine whether allowing the clock signal CK(n−1) to be delivered to the source/drain of the transistor T12. The drain/source and the gate of the transistor T11 both are electrically coupled to the source/drain of the transistor T12 to deliver the clock signal CK(n−1) to an node Q. The gate of the transistor T21 is electrically coupled to the node Q and on-off states of the transistor T21 are controlled by a control signal Q(n) on the node Q, the drain/source of the transistor T21 receives another clock signal CK(n), and the source/drain of the transistor T21 serves as an output terminal of the shift register SR(n) to output a gate driving pulse G(n) according to the received clock signal CK(n). Herein, Q(n−1) is the control signal on the node Q in the firstly-preceding (i.e., the nearest-preceding) stage shift register SR(n−1) (not shown). The pull-down circuit 100 is electrically coupled between the node Q and a gate-off voltage level Vss, and further electrically coupled to the source/drain of the transistor T21 to pull the gate driving pulse G(n) down to the gate-off voltage level Vss in a particular time duration.
FIG. 2 shows a timing diagram of multiple signals associated with the shift register SR(n) of FIG. 1, and an operation principle of the shift register SR(n) will be described below in detail with reference to FIGS. 1 and 2. Specifically, during the shift register SR(n) outputs the gate driving pulse G(n), the transistors T31, T32, T41, T42 in the pull-down circuit 100 are turned off. Whereas, during the shift register SR(n) stops outputting the gate driving pulse G(n), the voltage level of the gate driving pulse G(n) is pulled down to the gate-off voltage level Vss by the control signal Q(n) in the time duration of t.
However, when a manufacturing process variation of the transistors T41, T42 in the pull-down circuit 100 is excessively large, the control signal Q(n) in the time duration of t would be leaked to the gate-off voltage level Vss in advance rather than changes along the dashed line in the time duration of t in FIG. 2, so that the gate driving pulse G(n) would not be normally turned off and occurs a tail phenomenon (see the waveform of the G(n) in the time duration of t as illustrated in FIG. 2). If the tail is excessively long, pixels for displaying an image would be wrongly charged, resulting in abnormal image display.